comp.lang.vhdl Google Group

Re: Why doesn't this situation generate a latch?

wtx...@gmail.com (Weng Tianxiang) — Sat, 20 Mrz. 2010 02:28:12 UT

On Mar 19, 2:31 pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.co m>
wrote:
Hi,
Here is where you can find the contents:
[link]
1. /doc/OpenSPARCT2_SoC_Micro_Arc h_Vol1.pdf
2. /doc/OpenSPARCT2_SoC_Micro_Arc h_Vol2.pdf
3. There are too many reset descriptions. I just copy the most

Re: Why doesn't this situation generate a latch?

jonathan.brom...@mycompany.com (Jonathan Bromley) — Fri, 19 Mrz. 2010 21:31:48 UT

[Weng]
1. Reset that is asserted at the right time,
but has the wrong polarity, thus holding the design
in reset throughout your test.
2. Reset with the right polarity that is not asserted
reliably at power-up, because you were too cheap
to spend $0.70 on a power monitor/watchdog chip.

Re: Rusty with Configurations

jonathan.brom...@mycompany.com (Jonathan Bromley) — Fri, 19 Mrz. 2010 21:15:14 UT

Serves me right for having an obscure name. Next time
I'll arrange to be born "Sid" or "Bill" to keep it simple.
Seriously - I've long ago got used to more-or-less random
permutations of o, a and h in my name. The one mis-spelling
I squirm at is "John". Thanks for even taking the trouble
to notice!

Re: Why doesn't this situation generate a latch?

parekh...@gmail.com (fpgabuilder) — Fri, 19 Mrz. 2010 17:17:44 UT

Yeah! What are those?

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Re: vhdl for beginners

remill...@gmail.com (M. Norton) — Fri, 19 Mrz. 2010 14:52:07 UT

I'm not sure that's the lesson to take from Andy's explanation. If I
may be allowed to interpret here, you should use the data type that
fits the data you are representing by that symbol. If you are
shipping around numbers, use unsigned or signed as appropriate. If
you are shipping around discrete logic, use std_logic and

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Re: Awkward Arithmetic

gnu...@gmail.com (rickman) — Fri, 19 Mrz. 2010 14:25:11 UT

Gating (or enabling actually) a divider to adjust a clock rate will
give you the average rate you need, but it results in a jitter about
equal to the output clock period, i.e. 100%. Using a DCO results in
an output jitter equal to one reference clock period.
In my DCO the modulus is a power of two and there is no need to do

Re: Why doesn't this situation generate a latch?

gnu...@gmail.com (rickman) — Fri, 19 Mrz. 2010 13:32:38 UT

Ok, go ahead and tease us! Or are you going to share with us what the
six types are?
Rick

Re: Why doesn't this situation generate a latch?

gnu...@gmail.com (rickman) — Fri, 19 Mrz. 2010 13:32:06 UT

Yes, it was a typo... in other words, a mistake... Why do they call
it a "typo". It was a mistake regardless of how you categorize it.
Rick

Re: VHDL2008 generate syntax

han...@ht-lab.com (HT-Lab) — Fri, 19 Mrz. 2010 11:34:52 UT

Unfortunately this is not yet supported in Modelsim (not even the latest 6.5e
which was released last week :-(
Email your Mentor rep and ask him to open an ER,
Regards,
Hans
[link]

VHDL2008 generate syntax

trickyh...@gmail.com (Tricky) — Fri, 19 Mrz. 2010 10:17:59 UT

Im trying to use the new if/elseif/else generate syntax. Modelsim is
throwing up an error for me, but quartus 9.1 likes it:
test_gen : if test generate
g <= '1';
else
g <= '0';
end generate test_gen;
Modelsim 6.5 gives me the error: "Near Else - syntax error"
Same problem with the case version - quartus doesnt mind but modelsim

Re: Rusty with Configurations

martin.j.thomp...@trw.com (Martin Thompson) — Fri, 19 Mrz. 2010 09:56:53 UT

Or even "Jonathan" - sorry! That seems to be one of my natural typos - I'll
spell it right one day, honest :)
Martin

Re: vhdl for beginners

wipi...@gmail.com (vipin lal) — Fri, 19 Mrz. 2010 05:39:05 UT

hi andy.. that was some awesome information..I didn't find in any
sites these things.. I want to share this information in my blog.Hope
you don't mind.
I had little doubt about how successful I will be with writing codes
using only signed or unsigned data types.. but yesterday i wrote some
square root and division functions using numeric_std alone..it worked

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comp.lang.vhdl Google Group

Re: Why doesn't this situation generate a latch?

Re: Why doesn't this situation generate a latch?

Re: Rusty with Configurations

Re: Why doesn't this situation generate a latch?

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Re: vhdl for beginners

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Re: Awkward Arithmetic

Re: Why doesn't this situation generate a latch?

Re: Why doesn't this situation generate a latch?

Re: VHDL2008 generate syntax

VHDL2008 generate syntax

Re: Rusty with Configurations

Re: vhdl for beginners

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